1. Technical Field
Various embodiments relate to a semiconductor memory apparatus, and more particularly, to a nonvolatile memory apparatus.
2. Related Art
Dynamic Random Access Memory (DRAM) has advantages of high operating speed and low power consumption, but has a disadvantage of its volatile characteristic (i.e., losing information stored therein when power supply is cut off). On the other hand, Flash memory has advantages of its non-volatile characteristic (i.e., retaining information stored therein even though power supply is cut off), smaller size than a typical hard disk, and high resistance to physical impact, but has disadvantages of lower operating speed and higher power consumption than DRAM.
Recently, a variety of next-generation memory devices having the advantages of DRAM and Flash memory have been developed, and such devices may include a magnetic memory. The magnetic memory uses a resistance change resulting from a polarity change of a magnetic material to store a digital signal. Since the magnetic memory uses magnetism, the magnetic memory has excellent stability.
The magnetic memory generally includes a bit line, a word line, and a digit line parallel to the word line, and writes data using the vector sum of magnetic fields generated when currents flow through the bit line and the digit line at the same time. Since the magnetic memory includes the digit line in addition to the bit and word lines, the magnetic memory has a limitation in reducing a size of its memory cells. Furthermore, when one memory cell is selected to write data, some of the unselected cells may also be exposed to the magnetic fields generated to write the data in the selected memory cell. Thus, the data storage states of the unselected cells may be changed.
In order to solve the above-described issues, a spin transfer torque magnetoresistive random access memory (STT-MRAM) using a spin transfer torque (STT) phenomenon has been developed. The STT phenomenon occurs when a high-density current flows into a ferromagnetic substance whose magnetization direction does not coincide with the spin direction of the current. As a result, the magnetization direction of the ferromagnetic substance may be aligned with the spin direction of the current. A memory cell of the STT-MRAM typically includes one select transistor and one magnetic tunnel junction (MTJ) element, both of which are coupled between a bit line and a source line.
FIG. 1 illustrates an example of an MTJ element 10 applied to a conventional STT-MRAM. Referring to FIG. 1, the MTJ element 10 includes a first electrode layer as a top electrode, a second electrode layer as a bottom electrode, a pair of magnetic layers including a first ferromagnetic layer and a second ferromagnetic layer, and a tunneling barrier layer formed between the pair of magnetic layers.
The first ferromagnetic layer may include a free ferromagnetic layer of which the magnetization direction changes according to a direction of a current flowing through the MTJ element 10. The second ferromagnetic layer may include a pinned ferromagnetic layer of which the magnetization direction is fixed. A resistance value of the MTJ element 10 changes according to whether the magnetization direction of the free ferromagnetic layer is parallel or anti-parallel to that of the pinned ferromagnetic layer. Using such a change in the resistance of the MTJ element 10 according to the direction of the current, data 0 or 1 is written in the MTJ element 10.
FIGS. 2A and 2B are diagrams for explaining how data corresponding to logic low and high levels are written to the MTJ element 10, respectively. FIG. 2A is a diagram for explaining how the logic low level (e.g., data “0”) is written to the MTJ element 10. When the data “0” is written in a memory cell including a cell transistor CT and the MTJ element 10, a corresponding word line WL is enabled to turn on the cell transistor CT. Then, when a current flows in the direction from a bit line BL to a source line SL, (i.e., from the first electrode layer as the top electrode to the second electrode layer as the bottom electrode of the MTJ element 10, as indicated by the arrow in FIG. 2A), the magnetization direction of the first ferromagnetic layer (i.e., a free ferromagnetic layer) and that of the second ferromagnetic layer (i.e., a pinned ferromagnetic layer) become parallel. As a result, the MTJ element 10 has a low-resistance state, which corresponds to the logic low level.
FIG. 2B is a diagram for explaining how the logic high level (i.e., data “1”) is written to the MTJ element 10. Similarly, the corresponding word line WL is enabled to turn on the cell transistor CT. Furthermore, when a current flows in the direction from the source line SL to the bit line BL (i.e., from the second electrode layer to the first electrode layer, as indicated by the arrow in FIG. 2B), the magnetization direction of the first ferromagnetic layer and that of the second ferromagnetic layer become anti-parallel. As a result, the MTJ element 10 has a high resistance state, which corresponds to the logic high level.